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| copyright ? 1999, v3 semiconductor corp. v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 1 v370pdc rev. a0 high performance pci sdram controller with integrated peripheral control unit v3 semiconductor reserves the right to change the specifications of this product without notice. v370pdc is a trademark of v3 semiconductor inc. all other trademarks are the property of their respective owners. v370pdc sdram and prom isa conversion logic pci-to-isa conversion application v370pdc sdram sram/ flash pci target only application ? fully compliant with pci 2.2 specification target interface ? multiplexed or non-multiplexed 8-, 16-, or 32-bit generic peripheral bus interface ? support up to 1 gbyte of sdra ? support up to 2 single banks or 1 dual bank industrial standard 168-pin pc sdram dimm ? support up to 1kbyte of burst access from pci ? up to 5 programmable chip select for peripheral strobe generation ? large on-chip fifos using v3s unique dynamic bandwidth allocation? architectu e ? buffered pci clock output ? hot swap ready (picmg? hot swap specification) ? implementation of pci bus power management interface specification version 1.0 ? initialization through pci or serial eepro ? programmable pci and local interrupt management ? two 32-bit general purpose timers ? up to 66 mhz local bus clock with asynchronous pci clock up to 33mhz ? 3.3v operation with 5v tolerant inputs ? industrial temperature range (-40c to +85c) ? low cost 160-pin pqfp package the v370pdc pci sdram controller simplifies the design of pci based memory sub-systems. system designers can replace many lower integration support components wit this single, high-integration device saving design time, board area, and manufacturing cost. the v370pdc from v3 semiconductor is a high performance pci sdram controller with integrated peripheral control unit o perating at up to 66 mhz local bus speed. it features multiple address translation units from pci which allow designers the f reedom to customize their local address space. access latency of slower peripherals are absorbed through the large on- chip fifos. the peripheral bus provides low latency access t sdram. the peripheral control unit on the v370pdc also performs address decoding and chip-select strobes generation for sram, prom and other slow peripherals. the peripheral bus can also be tri-stated through a simple hand-shaking protocol to allow other local bus masters control of the bus. the sdram controller connects the pci bus through on-chip fifos to sdram arrays of up to 1 gbytes in size. the fully programmable sdram controller also supports the use of enhanced sdram to achiev even greater performance. burst accesses of up to 1 kbyte from pci is supported. the two general purpose 32-bit timers can be individually configured as a pulse width modulator, or used in other modes such as retriggerable or one- shot. interrupts for a real time os can be easily generated by the system heartbeat timer. a w atchdog timer is also provided for graceful recovery from catastrophic program failures. interrupt requests for all on-chip peripherals are m anaged by the interrupt control unit. additionally, off-chip interrupts can b routed to the interrupt control unit. the v370pdc is packaged in a low-cost 160-pin eija plastic quad flat pack (pqfp), and is available i 66mhz speed grade. t ypi c al applic atio
v370pdc 2 v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 copyright ? 1999, v3 semiconductor inc. this document contains the product codes, pinout, package mechanical information, dc characteristics, and ac characteristics for the v370pdc. detailed functional information is contained in the users manual. v3 semiconductor retains the rights to change docume ntation, specifications, or devic functionality at any time without notice. please verify that you have the latest copy of all documents before finalizing a design. 1.0 product codes 2.0 pin description table 2 below lists the pin types found on the v370pdc. table 3 describes the function of each pin on the v370pdc. table 1: product codes product code package frequency V370PDC-66 rev a0 160-pin eiaj pqfp 66mhz table 2: pin types pin type description pci i pci input only pin. pci o pci output only pin. pci i/o pci tri-state i/o pin. pci i/od pci input with open drain output. i/o 8 ttl i/o pin with 8ma output drive. i/od ttl input with open drain output. i ttl input only pin. o 2 ttl output pin with 2ma output drive. o 8 ttl output pin with 8ma output drive. o 12 ttl output pin with 12ma output drive. v370pdc copyright ? 1999, v3 semiconductor corp. v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 3 table 3: signal descriptions pci bus interface signal type r a description ad[31:0] pci i/o z address and data, multiplexed on the same pins. c/be[3:0] pci i bus command and byte enables, multiplexed on the same pins. par pci i/o z parity represents even parity across ad[31:0] and c/be[3:0] . frame pci i cycle frame indicates the beginning and burst length of an access. irdy pci i initiator ready indicates the initiating agents (bus masters) ability to complete the current data phase of the transaction. trdy pci o z target ready indicates the target agents (selected devices) abil- ity to complete the current data phase of the transaction. stop pci o z stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect). devsel pci o z device select, when actively driven by a target, indicates the driv- ing device has decoded its address as the target of the current access. idsel pci i initialization device select is used as a chip select during configu- ration read and write transactions. it must be driven high in orde to access the chips internal configuration space. perr pci i/o z parity error is used to report data parity errors during all pci transactions except a special cycle. serr pci i/od z system error is used to report address parity errors, data parity errors on the special cycle command, or any other system error where the result will be catastrophic. pclk pci i pclk provides timing for all transactions on the pci bus. sdram and peripheral bus interface signal type r description clkin i local clock input clkout o 12 x buffered pci clock output dcs [3:0] o 8 z sdram chip select ma[14:0] o 12 z sdram memory address (also, a[16:2] for peripheral access). ma[14:13] are typically used for ba[1:0] ras o 12 z sdram row address strobe v370pdc 4 v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 copyright ? 1999, v3 semiconductor inc. cas o 12 z sdram column address strobe mwe o 12 z sdram memory write enable mad[31:0] i/o 8 z sdram and peripheral bus data dqm [3:0] o 8 z sdram data mask (these act as mbe [3:0], a[1:0] for peripheral access) marb_in i peripheral bus arbitration input: treated as bus request input when v370pdc is the primary bus master. when v370pdc is the secondary bus master, this input acts as bus grant. marb_out o 8 0 peripheral bus arbitration output: treated as bus grant output when v370pdc is the primary bus master. when v370pdc is the secondary bus master, this output acts bus request. ale o 8 z address latch enable: used to latch the address on mad[31:0] during the address phase of a peripheral bus access. ads o 8 z asserted low to indicate the beginning of a bus cycle. blast o 8 z burst last. ready i data ready. wnr o 8 z write/read . sda i/od z serial eeprom data scl o 2 z serial eeprom clock ioc[11:0] i/o 8 z multi-purpose i/o that can be configured for many functions int [3:0] i/o 8 z general purpose interrupt inputs/outputs: may be used for either pci or local processor interrupts mode and reset signal type r description rstin i reset input: active low reset input used to initialize all internal functions of the chip. rstout o 8 0 reset output: driven active when the input reset is driven active. driven inactive when the rstout bit in the system register is set. the rstout signal is synchronous to the rising edge of clkin. ch i pci precharge bias: this signal is driven low to activate the on- chip precharge bias for use in picmg hot swap applications. non-hot swap applications should pull this signal high. table 3: signal descriptions (contd) v370pdc copyright ? 1999, v3 semiconductor corp. v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 5 2.1 pinout table 4 lists the pins by pin num ber. figure 1 shows the pinout for the 160-pin eiaj pqfp package and figure 2 shows the mechanical dimensions of the package mode i mode input: selects mastership of v370pdc : 0 = secondary master 1 = primary master power and ground signals signal type r description v cc - power leads for external connection to a 3.3v v cc board plane. gnd - ground leads for external connection to a gnd board plane. nc - no connect. a. r indicates state during reset. table 3: signal descriptions (contd) v370pdc 6 v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 copyright ? 1999, v3 semiconductor inc. table 4: pin assignments pin # signal pin # signal pin # signal pin # signal 1 rstin 41 vcc 81 vcc 121 vcc 2 pclk 42 ad14 82 mad9 122 ma5 3 gnd 43 ad13 83 ma13 123 mad27 4 vcc 44 ad12 84 mad10 124 ma4 5 nc 45 ad11 85 ma12 125 mad28 6ch 46 ad10 86 mad11 126 ma3 7ad3147ad987ma11127mad29 8 ad30 48 ad8 88 mad12 128 mad30 9ad2949c_be0 89 ma10 129 mad31 10 ad28 50 mode 90 gnd 130 gnd 11 ad27 51 gnd 91 mad13 131 ma2 12 ad26 52 ad7 92 ioc11 132 ma1 13 ad25 53 ad6 93 mad14 133 ma0 14 ad24 54 ad5 94 ioc10 134 ioc3 15 gnd 55 ad4 95 mad15 135 ioc2 16 c_be3 56 ad3 96 ioc9 136 ready 17 idsel 57 ad2 97 mad16 137 marb_out 18 ad23 58 ad1 98 ioc8 138 marb_in 19 ad22 59 ad0 99 mad17 139 ads 20 vcc 60 vcc 100 vcc 140 vcc 21 ad21 61 gnd 101 gnd 141 gnd 22 ad20 62 mad0 102 ma9 142 clkin 23 ad19 63 dcs0 103 mad18 143 ioc1 24 ad18 64 mad1 104 ma8 144 ioc0 25 ad17 65 dcs1 105 mad19 145 dqm3 26 ad16 66 mad2 106 ma7 146 dqm2 27 gnd 67 dcs2 107 mad20 147 dqm1 28 c_be2 68 mad3 108 ma6 148 dqm0 29 frame 69 dcs3 109 mad21 149 blast 30 irdy 70 mad4 110 gnd 150 wnr 31 trdy 71 gn d 111 ma d22 151 gnd 32 devsel 72 mad5 112 ioc7 152 clkout 33 stop 73 mwe 113 mad23 153 rstout 34 perr 74 mad6 114 ioc6 154 ale 35 serr 75 cas 115 ma d24 155 sda 36 par 76 mad7 116 ioc5 156 scl 37 vcc 77 ras 117 mad25 157 int0 38 c_be1 78 mad8 118 ioc4 158 int1 39 ad15 79 ma14 119 mad26 159 int2 40 gnd 80 gnd 120 gnd 160 int3 v370pdc copyright ? 1999, v3 semiconductor corp. v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 7 figure : pinout for 160-pin eiaj pqfp (top view) rstin# pclk gnd vcc nc ch# ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 gnd c_be3# idsel ad23 ad22 vcc ad21 ad20 ad19 ad18 ad17 ad16 gnd c_be2# frame# irdy# trdy# devsel# stop# perr# serr# par vcc c_be1# ad15 gnd gnd mad26 ioc4 mad25 ioc5 mad24 ioc6 mad23 ioc7 mad22 gnd mad21 ma6 mad20 ma7 mad19 ma8 mad18 ma9 gnd vcc mad17 ioc8 mad16 ioc9 mad15 ioc10 mad14 ioc11 mad13 gnd ma10 mad12 ma11 mad11 ma12 mad10 ma13 mad9 vcc 120 160 81 41 121 80 1 40 v370pdc vcc ma5 mad27 ma4 mad28 ma3 mad29 mad30 mad31 gnd ma2 ma1 ma0 ioc3 ioc2 ready# marb_out marb_in ads# vcc gnd clkin ioc1 ioc0 dqm3# dqm2# dqm1# dqm0# blast# wnr gnd clkout rstout# ale sda scl int0# int1# int2# int3# gnd ma14 mad8 ras# mad7 cas# mad6 mwe# mad5 gnd mad4 dcs3# mad3 dcs2# mad2 dcs1# mad1 dcs0# mad0 gnd vcc ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd mode c_be0# ad8 ad9 ad10 ad11 ad12 ad13 ad14 vcc v370pdc 8 v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 copyright ? 1999, v3 semiconductor inc. index pin 1 0.170.05 0.650.10 1.6typ 28.00.2sq 3.56max 0.300.10 40 41 80 81 120 121 160 31.20.4sq 0 `10 "p" 0.80.2 0.15 figure 2: 160-pin eiaj pqfp mechanical details v370pdc copyright ? 1999, v3 semiconductor corp. v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 9 3.0 dc specifications the dc specifications for the pci bus signals match exactly those given in the pci specification, rev. 2.2 section 4.2.1.1. for more information on the pci dc specifications, see the pci specification. 3.1 pci bus dc specifications table 5: absolute maximum ratings symbol parameter value units v cc supply voltage -0.3 to +3.6 v v in dc input voltage -0.3 to 6.0 v i out dc output current tba ma t stg storage temperature range -55 to +125 c table 6: guaranteed operating conditions symbol parameter value units v cc supply voltage 3.0 to 3.6 v theta ja thermal resistance tba c/w t a ambient temperature range -40 to +85 c table 7: pci bus signals dc operating specifications symbol parameter condition min max units notes v ih input high voltage 0.5v cc v cc + 0.5 v v il input low voltage -0.5 0.3v cc v i ih input high leakage current 0.7v cc m a1 i il input low leakage current 0 < v in < v cc + 10 m a1 v oh output high voltage i out = -500 m a0.9v cc v v ol output low voltage i out = 1500 m a0.1v cc v2 c in input pin capacitance 10 pf 3 c clk pclk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf 4 v370pdc 10 v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 copyright ? 1999, v3 semiconductor inc. notes: 1. input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state out- puts. 2. signals without pull-up resistors have greater than 3ma low output current. signals requiring pull resistors have greater than 6ma output current. the latter include frame , trdy , irdy , stop , serr , perr . 3. absolute maximum pin capacitance for a pci unit is 10pf (except for clk). 4. lower capacitance on this input-only pin allows for non-resistive coupling to ad[xx]. 3.2 local bus dc specification l pin pin inductance 20 nh table 8: local bus signals dc operating specifications (v cc = 3.3v+ 0.3v) symbol parameter condition min max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high leakage current v in = v cc -10 10 m a i il input low leakage current v in =gnd -10 10 m a v oh output high voltage i out = -2, -8, -12ma 2.4 v v ol output low voltage i out = 2, 8, 12ma 0.4 v i ozl low level float input leakage v ol = gnd -10 10 m a i ozh high level float input leakage v oh = v cc -10 10 m a i cc (max) maximum supply current tba ma i cc (typ) typical supply current tba ma c io input and output capacitance tba pf table 7: pci bus signals dc operating specifications symbol parameter condition min max units notes v370pdc copyright ? 1999, v3 semiconductor corp. v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 11 3.3 ac specifications the ac specifications for the pci bus signals match exactly those given in the pci specification, rev. 2.1, section 4.2.1.2. for more information on the pci ac specifications, including the v/i curves for 5v signalling, see section 4.2.1.2 of rev 2.1 pci specification. 3.4 pci bus timings table 9: pci bus signals ac operating specifications symbol parameter condition min max units notes i oh(ac switching current high 0v< v out 0.3 v cc -12v cc ma 0.3v cc v370pdc copyright ? 1999, v3 semiconductor corp. v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 13 notes: 1. applies only to ready pin when i960_rdy bit in lb_bus_cfg register is set to 1. table 12: local bus iming parameters for vcc =3.3 volts +/- 5% 66mhz # symbol description notes min max units 1t c clkin period 15 ns 2t ch clkin high time 5.5 ns 3t cl clkin low time 5.5 ns 4t su synchronous input setup 3 ns 4a t su synchronous input setup (ready )1tba ns 5t h synchronous input hold 1 ns 6t cov clkin to output valid delay 3 11 ns 7t czo clkin to output driving delay 3 11 ns 8t coz clkin to high impedance delay 4 12 ns 9t ale ale pulse width t ch +0.5 t ch +1 ns 10 t clh clkin rising to ale rising 2 10 ns 11 t ah clkin falling to ale falling 2 10 ns table 13: pci bus timing parameters for vcc = 3.3 volts +/- 10% # symbol description notes min max units 1t c pclk period 30 ns 2t su synchronous input setup to pclk 1 7 ns 3t h synchronous input hold from pclk 0 ns 4t cov pclk to output valid delay 2 3 11 ns 5t czo pclk to output driving delay 4 11 ns 6t coz pclk to high impedance delay 5 18 ns 7t rst reset period when prst used as input 16t c v370pdc 14 v370pdc_a0 data sheet rev 1.00 ds-pd01-0100 copyright ? 1999, v3 semiconductor inc. 3.6 serial eeprom port timings the clock for the serial eeprom interface is derived by dividing the pci bus clock. the waveforms generated are shown in figure 4. figure 4: serial eeprom waveforms and timing 4.0 revision history usa: 2348g walsh avenue santa clara, ca 95051 phone: (408)988-1050 fax: (408)988-2601 toll free: (800)488-8410 (canada and u.s. only) world wide web: http://www.vcubed.com table 14: revision histo r revision number date comments and changes 0.8 01/99 first pre-silicon revision of preliminary data sheet. 0.9 03/99 update figure 2: mechanical drawing; update table 8: local bus signals dc operating specifications; update table 10: local bus ac test conditions; update table 12: local bus signals ac operating specifications. 1.0 03/99 initial release. scl sda start condition stop condition 512 pci bus clocks 256 pci bus clocks 256 pci bus clocks |
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